Conference Program

 Note: Preliminary & subject to change.

Workshops & Tutorials (Feb 7 all day & Feb 8 all day)

Click here.

Sunday, Feb 9, 2015

Evening      Welcome Reception

Monday, Feb 9, 2015

8:30-8:50         Opening
8:50-10:00       Keynote: Paolo Faraboschi, HP Labs, The Machine
10:00-10:20     Break
10:20-12:00     Session 1.1:  Microarchitecture Exploration

Session chair: Paolo Faraboschi (HP)

“Exploring Architectural Heterogeneity in Intelligent Vision Systems”
Nandhini Chandramoorthy (The Pennsylvania State University), Giuseppe Tagliavini (University of Bologna), Kevin Irick, Siddharth Advani (The Pennsylvania State University), Antonio Pullini (ETH, Zurich), Sulaiman Al Habsi (Sultan Qaboos University), Vijaykrishnan Narayanan (The Pennsylvania State University), Luca Benini (University of Bologna), Jack Sampson, Matthew Cotter (The Pennsylvania State University)

“BeBoP: A Cost Effective Predictor Infrastructure for Superscalar Value Prediction”
Arthur Perais, André Seznec (INRIA)

“VSR Sort: A Novel Vectorised Sorting Algorithm and Architecture Extensions for Future Microprocessors”
Timothy Hayes, Oscar Palomar, Osman Unsal, Adrian Cristal, Mateo Valero (Barcelona Supercomputing Center)

“Increasing Multicore System Efficiency through Intelligent Bandwidth Shifting”
Victor Jimenez (IBM Research),  Alper Buyuktosunoglu (IBM Research), Pradip Bose (IBM Research),  Francis P. O’Connell (IBM Systems and Technology Group),  Francisco Cazorla (Barcelona Supercomputing Center),  Mateo Valero (Barcelona Supercomputing Center)

10:20-12:00     Session 1.2: Caches

Session chair: Aamer Jaleel (Intel)

“Exploiting Compressed Block Size as an Indicator of Future Reuse”
Gennady Pekhimenko,  Tyler Huberty, Rui Cai,  Onur Mutlu (Carnegie Mellon University), Phillip B. Gibbons, Michael A. Kozuch (Intel Labs),  Todd C. Mowry (Carnegie Mellon University)

“Talus: A Simple Way to Remove Cliffs in Cache Performance”
Nathan Beckmann,  Daniel Sanchez (MIT)

“Coordinated Static and Dynamic Cache Bypassing for GPUs”
Xiaolong Xie, Yun Liang (Peking University, China), Yu Wang (Tsinghua University, China), Guangyu Sun, Tao Wang (Peking University, China)

“Priority-Based Cache Allocation for Throughput Processors”
Dong Li (Qualcomm), Minsoo Rhu (NVIDIA), Daniel R. Johnson (NVIDIA), Mike O’Connor (NVIDIA / University of Texas at Austin), Mattan Erez (University of Texas at Austin), Doug Burger (Microsoft)
Donald S. Fussell (University of Texas at Austin), Stephen W. Keckler (NVIDIA / University of Texas at Austin)

12:00-13:30     Lunch

13:30-14:45     Session 2: Best Paper Session I

Session chair: Benjamin Lee (Duke)

Bamboo ECC: Strong, Safe, and Flexible Codes for Reliable Computer Memory”
Jungrae Kim,  Michael Sullivan,  Mattan Erez (The University of Texas at Austin)

“XChange: A Market-based Approach to Scalable Dynamic Multi-resource Allocation in Multicore Architectures”
Xiaodong Wang, José Martínez (Cornell University)

“Heterogeneous Memory Architectures: A HW/SW Approach for Mixing Die-stacked and Off-package Memories”
Mitesh Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel Loh (Advanced Micro Devices)

14:45-15:10    Break

15:10-16:50     Session 3.1: Mobile Computing and GPUs

Session chair: John Kim (KAIST)

“Event-based Scheduling for Energy-Efficient QoS (eQoS) in Mobile Web Applications”
Yuhao Zhu, Matthew Halpern, Vijay Janapa Reddi (UT Austin)

“Domain Knowledge Based Energy Management in Handhelds”
Nachiappan Chidambaram Nachiappan,  Praveen Yedlapalli (Pennsylvania State University),  Niranjan Soundararajan (Intel),  Anand Sivasubramaniam,  Mahmut Kandemir (Pennsylvania State University)
Ravi Iyer (Intel),  Chita R. Das (Pennsylvania State University)

“GPU Voltage Noise: Characterization and Hierarchical Smoothing of Spatial and Temporal Voltage Noise Interference in GPU Architectures ”
Jingwen Leng, Yazhou Zu, Vijay Janapa Reddi (The University of Texas at Austin)

“Mascar: Speeding up GPU Warps by Reducing Memory Pitstops”
Ankit Sethia,  Davoud Anoushe Jamshidi,  Scott Mahlke (University of Michigan)

15:10-16:50     Session 3.2: Cache Coherence and Superpages

Session chair: Dean Tullsen (UCSD)

“Hierarchical Private/Shared Classification: the Key to Simple and Efficient Coherence for Clustered Cache Hierarchies”
Alberto Ros (Universidad de Murcia), Mahdad Davari,  Stefanos Kaxiras (Uppsala Universitet)

“Flask Coherence: A Morphable Hybrid Coherence Protocol to Balance Energy, Performance and Scalability”
Lucia G. Menezo, Valentin Puente, Jose Angel Gregorio (Univ. de Cantabria)

“Prediction-Based Superpage-Friendly TLB Designs”
Myrto Papadopoulou, Xin Tong (University of Toronto),  Andre Seznec (INRIA),  Andreas Moshovos (University of Toronto)

“Supporting Superpages in Non-Contiguous Physical Memory”
Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé,  Rami Melhem (University of Pittsburgh)

16:50-17:15     Break

17:15-18:55     Session 4.1: Datacenters

Session chair: Vijay Janapa Reddi (UTAustin)

“Paying to Save: Reducing Cost of Colocation Data Center via Rewards”
Mohammad A. Islam, A.S.M. Hasan Mahmud, Shaolei Ren (Florida International University), Xiaorui Wang (The Ohio State University)

“Octopus-Man: QoS-Driven Task Management for Heterogeneous Multicore in Warehouse Scale Computers”
Vinicius Petrucci, Michael Laurenzano, Yunqi Zhang, John Doherty, Daniel Mosse, Lingjia Tang, Jason Mars (University of Michigan)

“Understanding the Virtualization ‘Tax’ of Scale-out Pass-Through GPUs in GaaS Clouds: An Empirical Study”
Ming Liu (University of Florida), Tao Li (University of Florida), Neo Jia, Andy Currid, Vladimir Troy (NVIDIA)

“Adrenaline: Pinpointing and Reining in Tail Queries with Quick Voltage Boosting”
Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, Ron Dreslinski, Thomas Wenisch (University of Michigan, Ann Arbor), David Meisner (Facebook), Jason Mars, Lingjia Tang (University of Michigan, Ann Arbor)

17:15-18:55     Session 4.2: Memory Architectures I

Session chair: Engin Ipek (Rochester)

“NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules”
Amin Farmahini-Farahani (University of Wisconsin-Madison), Jung Ho Ahn (Seoul National University), Katherine Morrow (University of Wisconsin-Madison), Nam Sung Kim (University of Wisconsin-Madison)

“Alloy: Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems”
Hao Wang (UW-Madison), Chang-Jae Park (Samsung Electronics), Gyung-su Byun (Southern Methodist University), Jung Ho Ahn (Seoul National University), Nam Sung Kim (UW-Madison)

“Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read”
Prashant J. Nair (Georgia Institute of Technology),  Chiachen Chou (Georgia Institute of Technology), Bipin Rajendran (Indian Institute of Technology – Bombay),  Moinuddin K. Qureshi (Georgia Institute of Technology)

“CAFO: Cost Aware Flip Optimization for Asymmetric Memories”
Rakan Maddah, Seyed Mohammad Seyedzadeh, Rami Melhem (University of Pittsburgh)

19:00-20:00     Business Meeting

Tuesday, Feb 10, 2015

8:00-9:40       Session 5.1: Industry Track

Session chair: Sudhanva Gurumurthi (AMD Research)

“Understanding GPU Errors on Large-scale HPC Systems and the Implications for System Design and Operation”
Devesh Tiwari, Saurabh Gupta, Jim Rogers, Don Maxwell (ORNL), Paolo Rech (Federal University of Rio Grande do Sul), Sudharshan Vazhkudai (ORNL), Daniel Oliveira (Federal University of Rio Grande do Sul), Dave Londo (Cray Inc.), Nathan Debardeleben (LANL), Philippe Navaux, Luigi Carro (Federal University of Rio Grande do Sul), Buddy Bland (ORNL)

“High Performing Cache Hierarchies for Server Workloads”
Aamer Jaleel, Joseph Nuzman, Adrian Moga,  Simon Steely, Joel Emer (Intel)

“Unlocking Bandwidth for GPUs in CC-NUMA Systems”
Neha Agarwal (NVIDIA and University of Michigan), David Nellans, Mike O’Connor, Stephen W. Keckler (NVIDIA), Thomas F. Wenisch (University of Michigan)

 “Understanding Idle Behavior and Power Gating Mechanisms in the Context of Modern Benchmarks on CPU-GPU Integrated Systems”
Manish Arora (AMD Research and UC San Diego), Srilatha Manne (Cavium Networks), Indrani Paul (AMD Research and Georgia Tech), Nuwan Jayasena (AMD Research), Dean Tullsen (UC San Diego)

8:00-9:40       Session 5.2: Interconnection Networks

Session chair: Andreas Moshovos (Toronto)

“Power Punch: Towards Non-blocking Power-gating of NoC Routers”
Lizhong Chen (Oregon State University),  Di Zhu,  Massoud Pedram,  Timothy M. Pinkston (University of Southern California)

“Augmenting Low-latency HPC Network with Free-space Optical Links”
Ikki Fujiwara (National Institute of Informatics), Michihiro Koibuchi (National Institute of Informatics), Tomoya Ozaki (Keio University),  Hiroki Matsutani (Keio University), Henri Casanova (University of Hawai at Manoa)

“SCOC: High-Radix Switches Made of Bufferless Clos Networks”
Nikolaos Chrysos (IBM Research — Zurich), Cyriel Minkenberg (IBM Research — Zurich), Mark Rudquist, Claude Basso, Brian Vanderpool (IBM Systems & Technology Group)

“Overcoming Far-end Congestion in Large-Scale Networks”
Jongmin Won, Gwangsun Kim, John Kim (KAIST), Ted Jiang (NVIDIA), Mike Parker (Intel), Steve Scott (Cray)

9:40-10:05      Break

10:05-11:45     Session 6.1: Fault Tolerance

Session chair: Pradip Bose (IBM)

“iPatch: Intelligent Fault Patching to Improve Energy Efficiency”
David J. Palframan, Nam Sung Kim, Mikko H. Lipasti (University of Wisconsin-Madison)

“Balancing Reliability, Cost, and Performance Tradeoffs with FreeFault”
Dong Wan Kim,  Mattan Erez (University of Texas at Austin)

“FTXen: Making Hypervisor Resilient to Hardware Faults on Relaxed Cores”
Xinxin Jin (University of California, San Diego), Soyeon Park (Whova),
Tianwei Sheng(Whova), Rishan Chen (University of California, San Diego),
Zhiyong Shan(University of California, San Diego), Yuanyuan Zhou(University
of California, San Diego)

“Correction Prediction: Reducing Error Correction Latency for On-Chip Memories”
Henry Duwe, Xun Jian, Rakesh Kumar (UIUC)

10:05-11:45     Session 6.2: Memory Architectures II

Session chair: Mike O’Connor (NVidia)

“Overcoming the Challenges of Cross-Point Resistive Memory Architectures”
Cong Xu (Pennsylvania State University),  Dimin Niu (Pennsylvania State University)
Naveen Muralimanohar (HP Labs),  Rajeev Balasubramonian (University of Utah and HP Labs)
Tao Zhang (Pennsylvania State University),  Shimeng Yu (Arizona State University)
Yuan Xie (University of California, Santa Barbara)

“Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case”
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, Onur Mutlu (Carnegie Mellon University)

“CiDRA: A Cache-inspired DRAM Resilience Architecture”
Jung Ho Ahn (Seoul National University), Nam Sung Kim (University of Wisconsin-Madison/AMD Research), Seongil O (Seoul National University), Young Hoon Son, Sanghyuk Kwon,  Sukhan Lee (Seoul National University),  David Palframan (University of Wisconsin-Madison)

“Tag Tables”
Sean Franey, Mikko Lipasti (University of Wisconsin – Madison)

11:45-13:15     Lunch

13:15-14:25     Keynote: Dharmendra S Modha, IBM, Brain-Inspired Computing

14:25-14:45     Break

14:45-16:00     Session 7: Best Paper Session II

Session chair: Josep Torrellas (UIUC)

“Architecture Exploration for Ambient Energy Harvesting Nonvolatile Processors”
Kaisheng Ma (PSU), Yang Zheng (PSU), Shuangchen Li (PSU), Karthik Swaminathan (PSU), Xueqing Li (PSU), Yongpan Liu (Tsinghua University), Jack Sampson (PSU), Yuan Xie (UCSB), Vijaykrishnan Narayanan (PSU)

“Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling”
Nathan Beckmann, Po-An Tsai, Daniel Sanchez (MIT)

“Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery”
Yu Cai,  Yixin Luo (Carnegie Mellon University), Erich Haratsch (LSI Corporation),  Ken Mai,  Onur Mutlu (Carnegie Mellon University)

16:00   Excursion

Wednesday, Feb 11, 2015

8:15-9:25       Keynote: David Wecker, Microsoft Research, Quantum Compilers

9:25-9:40      Break

9:40-10:55      Session 8.1: Best of CAL

Session chair: Jose Martinez (Cornell)

“Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing”
Carole-Jean Wu, Arizona State University

“Exploiting Webpage Characteristics for Energy-Efficient Mobile Web Browsing”
Yuhao Zhu, Aditya Srikanth, Jingwen Leng, Vijay Janapa Reddi (The University of Texas at Austin)

“vCache: Providing a Transparent View of the LLC in Virtualized Environments”
Daehoon Kim, Hwanju Kim, Jaehyuk Huh (KAIST)

9:40-10:55      Session 8.2: Modeling

Session chair: Lieven Eeckhout (Ghent University)

“GPGPU Performance and Power Estimation Using Machine Learning”
Gene Wu (The University of Texas at Austin), Joseph Greathouse (AMD), Alexander Lyashevsky (AMD), Nuwan Jayasena (AMD), Derek Chiou (The University of Texas at Austin)

“Quantifying Sources of Error in McPAT and their Potential Impacts on Architectural Studies”
Sam (Likun) Xi (Harvard University), Hans Jacobson (IBM), Pradip Bose (IBM), Gu-Yeon Wei (Harvard University), David Brooks (Harvard University)

“Studying the Impact of Multicore Processor Scaling on Directory Techniques via Reuse Distance Analysis”
Minshu Zhao, Donald Yeung (University of Maryland, College Park)

10:55-11:15     Break

11:15-12:30     Session 9.1: Accelerators

Session chair: Hadi Esmaeilzadeh (GATech)

“SNNAP: Approximate Computing on Programmable SoCs via Neural Acceleration”
Thierry Moreau, Mark Wyse , Jacob Nelson, Adrian Sampson (University of Washington), Hadi Esmaeilzadeh (Georgia Tech), Luis Ceze, Mark Oskin (University of Washington)

“BRAINIAC: Bringing Reliable Accuracy Into Neurally-Implemented Approximate Computing”
Beayna Grigorian,  Nazanin Farahpour,  Glenn Reinman (University of California, Los Angeles)

“Scalable Communication Architecture for Network-Attached Accelerators”
Sarah Neuwirth (University of Heidelberg), Dirk Frey (University of Heidelberg), Mondrian Nuessle (EXTOLL GmbH), Ulrich Bruening (University of Heidelberg)

11:15-12:30     Session 9.2: Security

Session chair: Mohit Tiwari (UTAustin)

“Understanding Contention-based Covert Channels and Using Them for Defense”
Casen Hunger,  Mikhail Kazdagli,  Ankit Rawat,  Alex Dimakis,  Sriram Vishwanath,  Mohit Tiwari (UT Austin)”

“Malware-Aware Processors: A Framework for Efficient Online Malware Detection”
Meltem Ozsoy, Caleb Donovick, Iakov Gorelik (Binghamton University), Nael Abu-Ghazaleh (University of California, Riverside), Dmitry Ponomarev (Binghamton University)

“Run-Time Monitoring with Adjustable Overheads Using Dataflow-Guided Filtering”
Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh (Cornell University)

12:30-12:45     Closing